Altium

Design Rule Verification Report

Date: 5/20/2020
Time: 2:17:32 PM
Elapsed Time: 00:00:03
Filename: C:\Users\Public\Documents\Altium\AD18\SLHR017B\SLHR017B_PCB.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.635mm) (InPolygon),(All) 0
Clearance Constraint (Gap=0.381mm) (All),(All) 0
Clearance Constraint (Gap=0.635mm) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=0mm) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=1.016mm) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=0.635mm) (InPolygon),(InPadClass('Jack')) 0
Clearance Constraint (Gap=0mm) (InComponentClass('FiducialMark')),(All) 0
Clearance Constraint (Gap=0.635mm) (InNetClass('HV_Net')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.1524mm) (Max=2.54mm) (Preferred=0.254mm) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=0.127mm) (MaxHoleWidth=0.508mm) (PreferredHoleWidth=0.3048mm) (MinWidth=0.127mm) (MaxWidth=1.016mm) (PreferedWidth=0.6096mm) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.254mm) (Max=2.54mm) (Prefered=0.254mm) and Width Constraints (Min=0.381mm) (Max=0.381mm) (Prefered=0.381mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.254mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.1524mm) (All) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=0.2032mm) (Max=6.3754mm) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.1016mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.01778mm) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Silk To Solder Mask (Clearance=0.127mm) (IsPad and InAnycomponent),(All) 0
Silk To Solder Mask (Clearance=0.1016mm) (All),(All) 0
Silk to Silk (Clearance=0mm) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk to Silk (Clearance=0.1016mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Component Clearance Constraint ( Horizontal Gap = 0.762mm, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0.508mm, Vertical Gap = 0.254mm ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 1.27mm, Vertical Gap = 0.254mm ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 1.27mm, Vertical Gap = Infinite ) (InComponentClass('Logo')),(All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 0